- 64-bit Arm® Cortex®-A53 processor used for quality-of-results (QoR) optimization and flow certification for Samsung’s 8LPP process
- Synopsys Design Platform provides comprehensive full-flow support for multi-patterning and full color-aware variation for the 8LPP process
- Certified, scalable reference flow compatible with Lynx Design System available through the Samsung Advanced Foundry Ecosystem (SAFE™) program
Synopsys, Inc. announced that Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, has certified the Synopsys Design Platform for Samsung Foundry’s 8-nanometer (nm) LPP (Low Power Plus) process. The Synopsys Design Platform provides comprehensive full-flow support for multi-patterning and full color-aware variation for the 8LPP process. Synopsys’ SiliconSmart® library characterization tool was key to developing the foundation IP used for this certification process and reference flow. This certification also includes a scalable reference flow compatible with Synopsys’ Lynx Design System with scripts for automation and design best practices, which is available through the Samsung Advanced Foundry Ecosystem (SAFE™) program.
The 64-bit Arm Cortex-A53 processor, based upon the Armv8-A architecture, was used for QoR optimization and flow certification. Key tools and features of the Synopsys Design Platform 8LPP reference flow include:
- IC Compiler™ II place-and-route: Multi-pattern and color-aware physical implementation flow with automated power ground (PG) synthesis and in-design IR-drop-aware refinement
- Design Compiler® Graphical RTL synthesis: Correlation, congestion reduction, and physical guidance for IC Compiler II
- DFTMAX™ and TetraMAX® II test: FinFET-based, cell-aware, and slack-based transition testing for higher test quality
- Formality® formal verification: UPF-based equivalence checking with state transition verification
- IC Validator signoff physical verification: High-performance DRC signoff, LVS-aware short-finder, signoff fill, pattern matching, and unique in-design verification for automated DRC repair and accurate timing-aware metal fill within IC Compiler II
- PrimeTime® timing signoff: Mode-merging, ultra-low voltage timing signoff with Advanced Waveform Propagation (AWP), Parametric On-Chip Variation (POCV) analysis, and placement rule-aware Engineering Change Order (ECO) guidance
- StarRC™ extraction: Multi-patterning, full color-aware variation, and 3D FinFET modeling
The certified, scalable reference flow compatible with Synopsys’ Lynx Design System is available through the Samsung SAFE™ program. The Lynx Design System is a full-chip design environment that includes innovative automation and reporting capabilities to help designers implement and monitor their designs. It includes a production RTL-to-GDSII flow that simplifies and automates many critical implementation and validation tasks, enabling engineers to focus on achieving performance and design goals. The Samsung SAFE™ program provides extensively tested process design kits (PDKs) and reference flows (with design methodologies) of Samsung Foundry.
