Researchers from CEA-List and CEA-Leti unveiled at ISSCC the first electro-optical router with dynamic, frame-level optical routing integrated with CMOS control logic, marking a major step toward practical optical networking inside advanced chiplet-based packages.
Their paper, “A 3.19pJ/bit Electro-Optical Router with 18ns Setup Frame-Level Routing and 1-6 Wavelength Flexible Link Capacity for Photonic Interposers”, demonstrates an electro-optical router implemented in 28 nm CMOS on a photonic interposer, capable of establishing optical paths in 18 nanoseconds. It dynamically selects one-to-six wavelengths per link, and achieves an energy efficiency of 3.19 pJ/bit with an active area of just 0.007 mm² per link.
Moving Optical Links Beyond Static Point-to-Point
Today’s optical interconnects are largely limited to static, point-to-point links, with initialization and training times ranging from microseconds to milliseconds. While suitable for board-level or rack-scale communication, those latencies prevent optical links from being used as a true networking fabric inside multi-die packages.
The router addresses this gap by integrating optical switching, routing control, serializer/deserializer (SerDes), and clocking logic directly with silicon photonics. The result is a dynamically routed optical interconnect that operates at nanosecond timescales, enabling optical communication across centimeter-scale interposers with responsiveness previously limited to short electrical links.
It supports frame-level routing, allowing optical paths to be established and torn down on demand, and adjusts link capacity dynamically by selecting between one and six wavelengths, according to application needs. This flexibility enables efficient use of optical bandwidth, while maintaining ultra-low latency.
Architecture and Implementation
The prototype is fabricated in a 28 nm CMOS process and integrated on a photonic interposer. Compact analog drivers, combined with standard-cell-based SerDes and clocking circuits, enable dense integration of optical endpoints close to compute and memory resources.
While the architectural target includes CPUs, GPUs, and high-bandwidth memory (HBM) in large 2.5D and 3D packages, the current chip serves as a proof of concept, demonstrated on a small-scale multi-die system derived from CEA-Leti’s earlier INTACT active interposer architecture (ISSCC 2020).
A First Integrated Dynamic Optical Routing
This is the first demonstration of dynamic optical routing in an integrated photonic switch that includes CMOS logic up to the protocol level. Previous optical switch demonstrations typically rely on standalone photonic devices with static or slowly reconfigured paths and do not integrate the full driving, control, and routing logic required for packet-level operation.
In contrast, the router operates as a miniature network switch inside the package, combining microring-based photonic devices with digital control logic to move data efficiently across the interposer. Compared with electrical routing fabrics or active interposers, the approach avoids power and latency penalties that scale with distance, relaxing constraints on data locality and enabling more flexible hardware architectures and software data placement.
Enabling New Chiplet Architectures
By bringing dynamic, ultra-low-latency optical networking into the package, the technology opens new possibilities for high-performance computing, AI accelerators, and data-intensive systems, where growing model sizes and memory demands increasingly stress conventional interconnects.
Rather than forcing all data to reside near compute cores to minimize electrical routing costs, dynamically routed optical links allow architects to treat memory and compute resources across the interposer as part of a unified, high-reach fabric without sacrificing latency or energy efficiency.
“As chiplet systems continue to grow in scale and complexity, the ability to move data efficiently across the entire package becomes essential,” said CEA-List’s Yvain Thonnart, lead author of the paper. “Our goal was to demonstrate that photonic links can provide that reach without sacrificing the flexibility designers expect from modern interconnects. This router is a step toward practical, dynamically routed optical networks that fit within standard CMOS design flows and real product constraints.”
For more information: www.cea.fr/english
