Simplicity Wins—Part 3: The Architecture Behind Efficient Active Balancing

Efficient Active Balancing Architecture for BMS:

Abstract

Simplicity and efficiency—achieving or balancing these two goals in a system-level circuit solution often requires simultaneous consideration of both hardware architecture and software algorithms. Active balancing exemplifies such a system-level solution. Designers must carefully select the appropriate ICs and components to implement energy transfer on the hardware side, while equally prioritizing the design of the active balancing strategy—the algorithm that governs the balancing process. This article delves into the architecture and algorithm behind efficient active balancing design for battery management systems (BMS).

Introduction

Building on the active balancing concepts previously introduced and discussed in this series, the following sections will continue the discussion by dividing the topic into two parts: the balancing architecture and the balancing algorithm. Together, these will examine the hardware and software design considerations behind a system-level active balancing solution that is efficient, streamlined, and easy to deploy and evaluate.

This article—Part 3 of the series—focuses on the balancing architecture. The design features a switch-matrix mainboard, two flyback power boards, a battery management system (BMS) control board, a microcontroller unit (MCU) evaluation board, and an isoSPI isolation communication evaluation board. The function of each hardware board will be briefly introduced in the following sections.

Switching Matrix Circuit Board

In active balancing design, charge needs to be transferred both between individual cells and between battery packs. As discussed in Part 2 of this series, a more efficient and streamlined balancing solution employs a multicell battery pack with two separate flyback circuits and two transformers—one dedicated to cell-to-cell balancing, and the other to pack-to-pack balancing. A switching matrix is used to selectively connect different cells to the active balancing circuit in a time-multiplexed manner.

The switching matrix in this active balancing architecture is built on the concept discussed earlier. It incorporates a 16-channel cell-selection matrix, enabling precise access to target cells for balancing. In addition, four polarity-selection switches are included to adjust voltage polarity when the selected cells are connected to the flyback circuit. The overall balancing architecture is illustrated in Figure 1.

In this architecture, a single flyback power stage is used to achieve cell-to-cell balancing by time-sharing one flyback converter across multiple cells within the battery pack. Any one of the 16 cells in the balanced pack can be selected for balancing.

The flyback stage is driven by the LT8306, a highly integrated and efficient controller that requires minimal external components—making it well-suited for isolated energy transfer in active balancing systems. By sourcing the module voltage directly from the balanced battery pack, duty-cycle variation during operation remains minimal even as individual cell voltages fluctuate. This enables near-constant current charging and discharging, resulting in more stable hardware performance and greatly simplifying the development and debugging of the active balancing algorithm, as summarized in Table 1.

Although, in theory, the module voltage Vmodule derived from N cells in the pack may not perfectly equal N × Vcell of any single cell, in practice a well-configured and properly operating active balancing system can maintain Vmodule ≈ N × Vcell with high consistency.

Vcell (V)	Duty Cycle (Cell Discharge)	Duty Cycle (Cell Charge)
4.2	0.5022	0.5172
4.1	0.5023	0.5176
4.0	0.5023	0.5181
3.9	0.5024	0.5185
3.8	0.5025	0.5190
3.7	0.5025	0.5195
3.6	0.5026	0.5200
3.5	0.5027	0.5205
3.4	0.5027	0.5211
3.3	0.5028	0.5217
3.2	0.5029	0.5224
3.1	0.5030	0.5231
3.0	0.5031	0.5238

Duty cycle (cell discharge) = (Vcell × N + VF) × NPS/(Vcell + (Vcell × N + VF) × NPS)

Duty cycle (cell charge) = (Vcell + VF) × NSP/(Vcell × N + (Vcell + VF) × NSP)

NPS = 1:N; NSP = N:1; VF = 0.3 V

Flyback Circuit Design and Simulation

Using the LT8306 in combination with a Würth transformer (part number 749119533) and the necessary passive components, an isolated flyback power stage is implemented as part of the active balancing architecture for energy transfer between cells.

Figures 2 and 3 present the LTspice^® schematic and corresponding simulation results for the flyback circuit used in this architecture. The simulations clearly demonstrate that the circuit achieves the intended bidirectional charge and discharge balancing for individual cells.

Boost Converter and Synchronous Rectification

Within this architecture:

• On the cell side, the LT8306 is powered from a regulated 7 V supply. Given that the maximum voltage of a single lithium-ion cell is 4.2 V, and the recommended operating range for this architecture is 3.0 V to 4.2 V, the 7 V rail is generated by boosting the cell voltage using an ADP1612 boost converter. This device is a cost-effective, high efficiency converter, well-suited for stepping up the low cell voltage in the balancing circuit to a level that ensures the LT8306 operates within its optimal range.
• During cell balancing charge, the flyback output matches the voltage of a single cell. At such low voltages and relatively high charge currents, using a diode for freewheeling would introduce significant losses and excessive heating—issues that become more severe as the cell voltage drops. Instead, pairing the LT8306 with a synchronous secondary controller such as the LT8309 provides a highly efficient conversion path while minimizing thermal stress, particularly in low voltage, high current conditions.

Figure 4 shows the complete LTspice simulation of the flyback power stage incorporating the ADP1612 boost converter and LT8309 synchronous rectification for active balancing.

Feedback Design Considerations

A critical factor when using the LT8306 for active balancing is the design of its feedback network. The total resistance along the path from the cell to the flyback circuit input—referred to as R_ROUTE—is generally non-negligible. This resistance comprises several contributors: the internal resistance of the cell, busbar resistance, harness wiring resistance, connector resistance, fuse resistance, PCB trace resistance, and the combined R_DS(ON) of six MOSFETs in series.

Depending on component choices, wiring harness quality, and actual assembly conditions, R_ROUTE can vary widely—from tens to several hundred milliohms. Its precise value usually requires on-site measurement. When multiplied by the average charging current (I_CHARGE), which can reach several amperes, the voltage drop across R_ROUTE may range from tens to hundreds of millivolts. When charging a cell, the secondary-side LT8306 operates at a relatively high switching frequency (Fsw). In this case, the time constant τ = R_ROUTE × C_INPUT, formed by the large routing resistance (R_ROUTE) and the large input capacitor (C_INPUT) of the flyback stage at the cell input, becomes significant. If this τ exceeds the flyback switching period (Tsw = 1/Fsw), and in particular if it exceeds the secondary LT8306 off-time (Toff), then by the time the LT8306 sample-and-hold error amplifier samples the secondary voltage, the voltage drop across R_ROUTE has not yet decayed to 0 V.

Therefore, when τ is large, the effect of this voltage drop must be incorporated into the calculation of the LT8306 feedback resistor network. While this drop is relatively small compared to the overall module voltage, it is significant relative to the voltage of an individual cell.

Therefore, when designing a battery charging circuit using the LT8306, it is essential to factor this voltage drop into the feedback resistor calculation. Compared to the formula given in the data sheet, the improved feedback resistor calculation becomes:

instead of the original:

R_FB = Feedback resistor
V_OUT = Output voltage
V_F = Output diode forward voltage
N_PS = Transformer effective primary-to-secondary turns ratio
V_ROUTE = Voltage drop across R_ROUTE

This adjustment ensures accurate voltage regulation and stable operation—especially under conditions of high cell-charging currents.

Pack-to-Pack Active Balancing Design

LTspice simulations and experimental validations were also performed for the pack-to-pack balancing scenario. Since the core operation closely resembles that of cell-to-cell balancing, only the simulation schematic and key results are presented here in Figure 5.

When implementing a voltage-based pack-to-pack balancing strategy, it is crucial to ensure that the balancing current path between battery modules does not pass through the pack’s main terminals (V+ and V–). This precaution prevents interference with the measurement of the overall pack voltage—whether measured directly across V+ and V– or calculated by summing the voltages of individual cells from cell 1 to cell 16.

The influence of various wiring methods on pack voltage measurement accuracy is illustrated in Figure 6, while the recommended connection scheme for pack-to-pack balancing is shown in Figure 7.

BMS Control Board

Active cell balancing fundamentally relies on the BMS and, more specifically, on the capabilities provided by the BMS’s cell monitoring unit. Within an active balancing architecture, the cell monitor plays several essential roles, including:

1. Real-time monitoring of each cell’s status—tracking voltage, temperature, and protection limits such as overvoltage and undervoltage conditions.
2. Open-wire fault detection and diagnostics—ensuring overall system safety and reliability.
3. Balancing switch control—acting as the I²C master to interpret balancing commands received from the MCU via isoSPI and forwarding them to the I/O expander chip, managing read/write operations as needed.
4. Balancing status management—handling reading and writing of operational data to onboard EEPROM via I²C.
5. Daisy-chain communication—facilitating data transmission in a daisy-chain configuration to minimize the required number of MCUs.

While these responsibilities only represent a subset of the cell monitor’s functions in the active balancing circuit, they clearly highlight its critical role.

In this architecture, the ADBMS6830B is deployed as the BMS control unit. This high performance multicell battery stack monitor supports measurement of up to 16 series-connected cells, maintaining a lifetime total measurement error (TME) under 2 mV across the full temperature range. This enables precise, real-time voltage monitoring of all 16 cells in the balanced battery pack.

With an input measurement range from –2 V to +5.5 V, the ADBMS6830B is compatible with diverse cell chemistries—from high voltage lithium nickel manganese cobalt oxide (NMC) cells to lower voltage LiFePO₄ cells—offering deployment flexibility across various battery types. Moreover, all cells can be sampled simultaneously and redundantly via two independent ADCs, ensuring highly accurate and reliable voltage data for the balancing algorithm to function effectively.

MCU Evaluation Board

In this architecture, the MAX32670 is chosen as the primary control unit. Unless otherwise specified, all subsequent references to MCU denote the MAX32670. This ultra low power, cost-effective, and highly reliable 32-bit microcontroller provides the processing headroom required for complex sensor and control tasks, making it well suited for industrial and IoT applications.

In this active balancing architecture, the control logic is distributed across two principal locations:

1. Host-side control—the active balancing GUI running on a PC.
2. Embedded control—the firmware executing on the MCU.

The MCU communicates with the host GUI via UART and interfaces with the BMS over SPI; commonly, an isoSPI module is employed to provide electrical isolation and improve communication robustness. The MCU also utilizes internal peripherals such as timers and GPIOs to manage timing, state control, and I/O functions within the balancing process.

Instead of designing a custom MCU board at this stage, the architecture employs the MAX32670EVKIT evaluation board. This expedites development by allowing firmware and driver code to be written and debugged using the SDK, programmed into the MCU’s flash, and validated alongside the active balancing GUI—enabling full function system validation without needing a custom MCU PCB in the early phases.

isoSPI Isolation Communication Evaluation Board

Within this architecture, the DC2792B isolation communication evaluation board, based on the LTC6820, is selected to facilitate communication between the MCU and the cell monitor. The LTC6820 supports bidirectional SPI communication over a single twisted-pair cable between two electrically isolated devices.

During operation, it converts the MCU’s 4-wire SPI signals into 2-wire isoSPI pulse signals for transmission to the cell monitor, and conversely decodes isoSPI signals received from the cell monitor back into standard 4-wire SPI signals for the MCU.

Although not strictly mandatory, the LTC6820’s isolation capability significantly enhances system reliability and safety by electrically isolating high and low voltage domains. This protects the battery pack, BMS control circuitry, and MCU hardware, while also improving safety for system developers and end users by minimizing high voltage risks. For these reasons, the LTC6820 is strongly recommended in this architecture.

SOC Calculation During Balancing

This architecture achieves a near constant-current charging and discharging process for cell balancing, significantly simplifying the estimation and monitoring of the state of charge (SOC) during balancing. Typically, users only need to track three key parameters: balancing duration, balancing state (charging or discharging), and the premeasured balancing current—since this architecture maintains a near constant current throughout the balancing process. Using these, an approximate SOC estimation can be obtained, eliminating the need for dedicated coulomb counter ICs.

Of course, for applications requiring higher precision SOC calculations during balancing, the use of a coulomb counter remains the most accurate approach.

Physical Demonstration of the Active Balancing Architecture

The physical implementation of this architecture is shown in Figure 8 to Figure 11 below, illustrating the hardware setup used to realize active balancing in a 16-cell battery pack.

Conclusion

This article focused on the design of an efficient and streamlined active balancing hardware architecture, emphasizing the careful selection and integration of key ICs and hardware boards that make the solution possible. These components were thoughtfully chosen to create a simple yet effective active balancing system.

In the next article, we will delve into the algorithm design behind an efficient active balancing solution for BMS.

Read other articles in this series:
Simplicity Wins—Part 2: Discovering an Efficient Active Balancing Solution for BMS Design
Simplicity Wins—Part 1: A Deeper Look into Active Balancing on BMS