A tantalizing need for faster, smaller and secure memories is driving the industry to leave no stone unturned in creating some cutting-edge tools for better storage. The requirements for memory is different for Industry 4.0. As there are perspectives on embedded memory for IoT, robotics, and wearables, a detrimental trade-off between the size, power consumption, and speed becomes a concern. Additionally, the overhead of the processor’s attributes has a causative effect on integrating memories. Embedded technology also calls for better monolithic technologies with in-built security mechanisms.
Keeping this in mind, we thought of sketching a detailed painting of the memory world. In this two-part article, we first focus on the different aspects of Random-Access memories, which have long forgotten the bookish definition of being volatile. In the second issue, we discuss Read Only Memories and the challenges face in embedded memories.
1. MRAM – Magneto-resistive Random-Access Memory
This is a non-volatile form of memory (oxymoron, considering most of us have heard of RAM’s being volatile). It was ideated in the early 1960s. It took nearly 50 years to produce a minimal 4MB worth of memory. They follow the conventional memory structure of a transistor followed by a memory element.
The memory element is a sandwiched structure not unlike a capacitor. The gap is entrenched with an insulating material ( to follow the analogy- a dielectric in a capacitor). This forms a magnetic tunnel junction – MTJ.
One of the plates acts as a reference- it is permanently magnetized using a magnet. The other plate is the deciding factor. The transistor which acts as a switch controls the magnetization of the plate and hence changes its electrical resistance. It is known as the magnetoresistance effect.
A simple cross-correlation between electrostatic laws will conclude that when current is in the same direction of the magnetic field the resistance increases and vice- versa. Tunnel magnetoresistance refers to the ability of electrons tunneling through the MTJ when the magnetization in the two plates are parallel.
How does TMR work?
It is really easy to make an MTJ- just take two ferromagnetic materials, separate them with an extremely thin insulator- in the range of hundreds of Angstroms. It is more of a wave-like phenomenon (De- Broglie you ruined it for me). The top plate is called the free plate, the bottom one becomes the reference.
The nature of the current in the ferromagnetic material is composed of partial currents made of spin up and spin down electrons. The spin of the electron gives rise to the magnetic effect. In turn, the currents generated consist of partial spins in each of them.
The tunneling process is conservative of spin. The origin is due to the difference in the density of states across the barrier. A change in magnetization results in exchange in DOS of the two spins across the barrier. Thus, in parallel magnetization, the resistance is lesser than in ant-parallel magnetization. The older MRAM type called the toggle MRAM used a magnetic field to toggle between the two resistances. Hence it was called Toggle MRAM.
- Density: It is high as the makeup is one transistor and a memory element, along the lines of 1T1C DRAM.
- Speed: On average write and read can happen at 30ns comparable to SRAM.
- Power consumption: The energy consumed is 27.2uJ for 10 acquisitions per second. It is figuratively 15 times lesser than serial Flash.
- Data retention: MRAM is a non-volatile memory. But as the current reduces, the memory degrades.
- Cost: It is inexpensive as the density is higher and is a good alternative to SRAM.2. Re RAM: Resistive Random-Access Memory
2. ReRAM – Resistive Random-Access Memory
Re RAM was a promising phenomenon in the early 2000s. It was a fad turned patent competition between companies as a replacement for the Flash drives. But as the development could not be driven rapidly, it slowed the progress to an evanescent stage. Fast forward, looking at the embedded technology boom, ReRAM is again seeing the light of the day. It has an edge over other memory elements in terms of power. You can envisage IoT based applications.
The structure is based on resistive switching. It consists of a dielectric sandwiched between two electrodes. These dielectrics will have conducting filaments which are used to store data. It is much simpler in principle compared to the MRAM, but less conducive for commercialization.
How does Resistive Random-Access Memory work?
The underlying principle is of memristors. The resistance exhibited is a function of the history of current which had flown through the device. Touted as the “missing circuit element”, it is has been postulated as the fourth fundamental electrical device after the Resistor (R), Inductor (L), and the capacitor (C). Quoting an analogy- the memristor is a radius-dynamic pipe. When water flows in one direction, the radius increases, and resistance decreases. Vice-versa too. After the motor stops, the pipe does not revert to its original state, it is not elastic.
Similarly, when a few high dielectric constants were subjected to electric fields that switched between the thresholds of dielectric breakdown and insulation, the device behaves, switched between low and high resistance. To achieve a conductive filament, defects are introduced in the crystal structure. The defects can be easily incubated in the metal oxide structures.
The basic form of defects is analogous to the holes in a p-type semiconductor. At voltages/currents near the breakdown, the defects which may reach high concentrations form conducting sub band structures. The conductive element is SET. At lesser electrical pressures, the path is broken or RESET. The resistance peaks. There are two kinds of formation and deformation- unipolar and bipolar.
It is known that the Conduction Filament is conical in structure, with the tapered end near the cathode. Since it is a memristor, constant stress is not required to maintain the structure. As a result, the device is non-volatile. A crucial problem is the sneak current present.
The specifications change based on the type of dielectric used. The below mentioned are for HfO2.
- Speed: Less than 0.3 ns switching time.
- Power Consumption: Current consumption less than 30uA.
- Endurance: Around 100 percent up to 10 billion cycles.
- Size: Highly scalable in nanometer-scale with capacity at 1TB.
- It also provides better security and prevents memory cell extraction.
3. PcRAM: Phase-change Random-Access Memory
PcRAM is also non-volatile. The initial research for the use of phase changing substances in memory started in academia and moved to Industry. However, difficulties in implementation and high cost deterred enthusiastic research. The structure consists of chalcogenide glass, which expresses different resistances based on its crystal structure.
Currently, the type of chalcogenide used is called GST(easy to remember!)- Germanium, Antimony, Tellurium- an alloy. In a few cases, the phases achieved can be more than binary- which allows for greater storage capabilities. For example: if the number of phases achieved is 4, the total number of bits that can be stored in a single structure can be 2.
How does Phase Change RAM work?
The chalcogenide glass is sandwiched between two electrodes. An insulator may also be provided for the concentration of heat. Right after the fabrication of the memory, the inertial state is that of crystalline structures. The application of extensive heat at the end of fabrication renders it so. The crystalline structure- is an organized lattice, which allows for easy movement of electrons between cells. It becomes the SET state and has low resistance.
Electric current is used to produce the heating effect and destroys the crystalline structure. The resultant amorphous mess produces the RESET state of high resistance. The SET and RESET states correspond to bit 1 and 0 respectively. To revert to the SET state, the substance is heated beyond the crystallization temperature but below the melting point. While reading the resistance of the cell, the lower current is used to preserve the state. The access devices, usually MOSFETs are used which limits the current. The access device size is the limiting factor of the density of the memory cell.
The memory device, in itself, occupies lesser space. One of the major issues is the power consumption. To reach the amorphous state, high-temperature heating followed by rapid cooling is required. This calls for high currents. However, the amorphous to crystalline states need lesser currents. The high current consumption is a cause of concern when the entire memory world is looking for Wattage in nanoscale. The fabrication cost of PcRAM is impressively less. There is also a trade-off between the stability of the state and the time needed to operate it. Crystalline state is inherently less stable than their counterparts. But if the challenge of power is overcome, they will prove as one of the promising changes to memory technology.
- Speed: For byte accessing the read latency is 78ns and the write latency is 430ns.
- Power: The current required stands at 1000s-1500s of microamperes. The standby power is less.
- Size: Scalability is high as it does not use a floating gate structure. As a result, the density also increases.
- Cost: As the density of the cell is higher, the cost is significantly lower.
- Endurance: The write endurance is lesser than SRAM but greater than NAND Flash. It is in the orders of 108 – 1012.
The focus of the article relies on the physics behind the technologies. As the information about the specifications varies based on the implementation, we have given a general estimate than the specific numbers to avoid bias. The sources which have been used are research papers from different organizations.
Disclaimer: Science is easy if you know English. English is easy if you have sense. Anything is suggestive.