The MIPI Alliance announced the first update to its publicly available, royalty-free, MIPI I3C Basic specification. Version 1.1.1 dramatically enhances the speed and flexibility of I3C Basic, simplifying development of innovative designs for products such as smartphones, wearables, and systems in automobiles and server environments.
As the successor to the legacy I2C interface, MIPI I3C/I3C Basic provides a scalable, medium-speed, utility and control bus interface for connecting peripherals to application processors, streamlining integration and improving cost efficiencies. The specification uses a two-wire interface and supports in-band interrupts, resulting in a smaller printed circuit board (PCB) footprint compared with other control bus solutions. I3C can be used to integrate a vast array of peripheral devices and sensors to application processors.
Available for implementation without MIPI Alliance membership, I3C Basic is a subset of the full MIPI I3C specification that bundles the features most commonly needed by developers and other standards organizations.
The updated version of I3C Basic provides for extensible use of extra bus lanes to increase the interface speed to nearly 100 MHz, future-proofing the interface for rising speed requirements. The new version includes two High Data Rate (HDR) modes — HDR Double Data Rate (HDR-DDR) and HDR Bulk Transport (HDR-BT) — which are designed to transfer more data at the same bus frequency:
- HDR-DDR with support for common command codes (CCCs) and flow controls doubles the raw data rate to 25 Mbps over a single lane compared with I3C Basic’s Single Data Rate (SDR) mode.
- HDR-BT with CCC support delivers efficient bulk transport of data over up to four lanes. It can enable raw data rates of up to 100 Mbps.
Another feature added to I3C Basic v1.1.1 was standardized target reset, which enhances the specification’s ability to reset a specific peripheral device, enabling better recovery from error conditions. This mechanism allows a controller to reset one or more selected targets and avoid resetting any others; supports different levels of reset, ranging from resetting only an I3C peripheral within a target to resetting the whole target device; and supports I3C’s error-escalation mechanism, including reset of an errant target.
“The new version of I3C Basic is more closely aligned with the core I3C specification so that the mobile ecosystem and broader system-integrator community can more effectively and efficiently implement it within an ever-greater variety of applications,” said Joel Huloux, chairman of MIPI Alliance. “With these updates, we continue to strengthen the upgrade path from I2C and advance I3C as the universal utility and control bus.”
I3C Basic has also been the centerpiece of several industry collaborations. It was adopted by JEDEC in its Sideband Bus and DDR5 standards, and is an area of focus for MIPI liaison relationships with DMTF (Distributed Management Task Force), ETSI (European Telecommunications Standards Institute), and TCA (Trusted Connectivity Alliance). The original I3C v1.0 specification was the result of extensive multi-year industry collaboration, particularly with the MEMS & Sensors Industry Group.
In conjunction with the release of I3C Basic v1.1.1, MIPI Alliance also updated the core I3C specification, now v1.1.1 and available only to members, to provide clarifications and additional details to the previous version. Both I3C and I3C Basic v1.1.1 were also revised to replace offensive terms with ones that more accurately reflect the functions of technical devices.
A variety of system-solution resources have been introduced to aid developers and support the growing I3C ecosystem:
- MIPI Discovery and Configuration (MIPI DisCo) for I3C, a software framework designed to simplify software integration of sensors and other peripherals that use the I3C/I3C Basic device interface, by allowing major operating systems to identify MIPI-conformant external devices in mobile and mobile-influenced systems and automatically implement drivers for them
- MIPI I3C Host Controller Interface (HCI), a common set of capabilities for the host controller and the software interface
- MIPI I3C HCI driver for Linux, defining device-specific operations for compliant MIPI I3C host controller hardware implementations from multiple vendors
- MIPI Debug for I3C, a bare-metal, minimal-pin interface for transporting debug controls and data between a debug and test system (DTS) and target system (TS)
The MIPI I3C Working Group recently presented the webinar, “What’s New in MIPI I3C Basic and the I3C Ecosystem,” which is now available on demand. The upcoming MIPI DevCon virtual event (Sept. 28-29) will also offer presentations and a panel discussion focused on the latest developments in the world of I3C.
In addition to these education opportunities, several new resources have been made available, including a Conformance Test Suite for I3C/I3C Basic, updated FAQs, and two application notes – one focused on I3C’s Hot-Join feature and the second on integrating virtual devices and targets.