The embedded processor market underwent a significant shift when Arm entered the arena. Up until that point, 32-bit microcontrollers were not very common, and 8-bit architectures still dominated. There was also a lot of fragmentation in the market, which meant developers were often committed to a proprietary instruction set architecture (ISA). But once semiconductor manufacturers starting licensing and deploying Arm’s Cortex-M core IP, the shift to 32-bit with a common ISA was underway and there would be no stopping it.
The IoT accelerated that shift, and it has been many years since any other ISA has even attempted to challenge Arm’s dominance in the embedded space. In the enterprise space, x86 is the dominant ISA, which means Intel and AMD are the leading suppliers. While Arm is attempting to shake that up, the ISA that is making an impact in both application areas is the RISC-V architecture. This open-source and extensible processor IP is completely free to use, so it is not surprising that it is turning heads.
The importance of the ISA
The instruction set architecture, or ISA, defines the real-world interface between hardware and software. Whatever the high-level programming language used, it will ultimately be converted into low-level machine code, the actual bits, and bytes that trigger activity in the processor’s hardware elements, such as multipliers and accumulators, shifters, and adders. The way the ISA is defined and implemented is fundamental to the way the processor behaves and the performance it offers.
While in its simplest form, a processor is a conglomeration of arithmetic and logic units that are controlled using simple binary digits, using this concept in any practical way quickly introduces architectural complexity. To tackle this complexity, processor architects favour one of two basic approaches; the complex instruction set computer (CISC) and the reduced instruction set computer (RISC). A processor based on a CISC architecture will feature instructions of variable size, with many programming modes. A RISC architecture typically uses instructions of a fixed size and offers fewer programming modes.
Of the two, RISC variants are by far the more numerous, but CISC can deliver higher performance. The choice of which to use comes down to balancing ease of use against capability. In general, a RISC architecture is simpler to program but perhaps less capable than a CISC architecture. However, for the majority of applications, ease of use wins the argument, which is why most general-purpose processors available adopt the RISC approach. By contrast, the x86 architecture uses a CISC approach, but although x86 based processors are widely available, their use is largely focused on computers and servers, where the needs are relatively focused on data processing. This compares to the IoT and other devices with disparate requirements, where a RISC architecture would normally be used.
What makes a good RISC ISA?
Bus width is another factor, as this defines the size of the instruction or operator, and the data, or operand, that can be processed in a single clock cycle. The nature of RISC lends itself to bus widths of various sizes. For example, an 8-bit processor would be able to read (fetch) an 8-bit value (instruction or data) in one memory access (cycle), which essentially delimits the number of operations that can be executed in one cycle to the total number of bits in the bus. For relatively simple microcontrollers, 8-bit buses are still adequate. It follows that a 16-bit, 32-bit or 64-but bus would be able to encode and fetch comparatively more instructions in a single cycle.
The way the instructions handle data will also vary based on the addressing mode. For example, some instructions will operate on the data retrieved, while others will use the operand as the memory address to point to the data to be used. the way these addressing modes are triggered is controlled by the instruction, which means there are normally several versions of the same instruction (such as ‘add’) that can be used with different addressing modes.
Most of these subtleties are hidden from the designer through the abstraction of software. High-level languages, such as C, do not make it obvious what addressing mode is used, that decision is left to the underlying tools, such as the compiler. It is these tools that take the high-level program and convert it to low-level machine code.
This low-level dependency on the underlying hardware architecture makes it difficult to port code between ISAs. The use of higher levels of abstraction (for example, C) does go a long way towards addressing that dependency and lack of portability, but it remains a major factor in embedded design. For this reason, design teams will often choose an ISA and stay with it for the duration of a project and even across many projects when the same embedded software is used.
The Arm ISA disrupted this status quo by providing low-level compatibility between processors from multiple vendors, but other ISAs (many proprietaries) remain. Many competing processor vendors are now Arm licensees and will offer an Arm-based product line, while still maintaining products based on other ISAs. This also means maintaining the toolchain that allows those ISAs to be used. toolchains can represent a significant investment for processor vendors, but the competitive advantage of offering a proprietary ISA would outweigh the additional effort.
Open-Source could change everything
The support needed by an ISA is delivered through the toolchain. When other vendors also contribute to that toolchain it is generally referred to as an ecosystem. While the ISA vendor would normally govern the ecosystem, it can relieve the pressure on the ISA vendor to have third parties offering solutions. The more semiconductor vendors offering products based on the same ISA, the more likely it is to attract tool vendors to support it, as the total number of end customers would justify a large and diverse ecosystem focused on the architecture. This is the case with Arm’s Cortex-M in the embedded sector, where there is now a strong ecosystem based around its ISA.
Open-source projects can attract similar interest from third-party tool providers. Linux, for example, is a popular open-source operating system in both the enterprise and embedded sectors, and it is widely supported by companies offering commercial tools to support software development based on the Linux operating system. The appeal of open-source often lies in two areas; it is generally free to use the technology, and the user is free to modify it. This can provide a great deal of flexibility and potential cost savings.
While open-source software is now widely used in commercial products, open-source hardware is also making an impact. The open-source ISA, RISC-V, is a good example of this. The RISC-V ISA appeared in 2010, initially developed as an academic research project by the University of Berkeley. By 2015 a group of semiconductor vendors with a commercial interest in an open-source ISA formed the RISC-V Foundation. Now known as RISC-V International, the global non-profit organisation now has over 1,000 members in more than 50 countries.
Before RISC-V International provided the framework to take an open-source ISA into the commercial arena, there had been little innovation in the area of processor architectures. Given that the entire modern world relies on software running on processors, this may seem a little incredulous. It may also be the main reason why RISC-V has garnered so much interest in recent years. Now, with the massive trend towards deploying artificial intelligence (AI) and machine learning (ML) everywhere, the interest in a royalty-free and extensible ISA is completely understandable.
First steps with RISC-V
The RISC-V International organisation supports the use of the IP in many ways. As an open-source project, members contribute their version of the core to the project and there are now more than 100 versions of the ISA available for use in ASICs, FPGAs, and SoCs.
The FE310 is an early example of an SoC based on the RISC-V architecture, developed by SiFive using its E31 standard core and supported by its HiFive development boards. Another is the GD32VF103 SoC from fabless semiconductor company, GigaDevice. Its device forms the basis of the Seeed Studio Sipeeed Longan Nano development board. Microchip also offers a development board for RISC-V evaluation, which is based on its PolarFire SoC FPGA. The Icicle Kit can run an off-the-shelf Linux distribution on the RISC-V processor subsystem in the FPGA, and the board also offers expansion ports compatible with Raspberry Pi and mikroBUS.
The extensible nature of the RISC-V IP offered as open-source technology means developers cannot only implement the core in their choice of platform but to add new instructions to the architecture. This accurately illustrates the flexibility open-source technology offers, while the governance provided by RISC-V International ensures the project will continue to excite and enable developers for many years to come.
With more interest in the acceleration of AI and ML at the processor level, the potential for RISC-V to help shape this new era of processor development cannot be overlooked. As the supporting ecosystem for RISC-V also grows, developers can look forward to innovations shortly.