Renesas Electronics and ASTC Accelerate Software Development for Smart Cameras with Virtual Platform for R-Car V3M

PC-Based VLAB/IMP-TASimulator Contributes to a Significant Reduction in Development Time and Improvement in Software Quality

Renesas Electronics Corporation, a premier supplier of advanced semiconductor solutions, Australian Semiconductor Technology Company Pty Ltd (ASTC), and VLAB Works, a subsidiary of ASTC, announced a joint development of the VLAB/IMP-TASimulator virtual platform (VP) for Renesas’ R-Car V3M, an automotive system-on-chip (SoC) for advanced driving assistance systems (ADAS) and in-vehicle infotainment systems. The VP simulates image recognition and cognitive intellectual properties (IPs) in the R-Car V3M SoC and realizes embedded software development using a PC only, which enables the VP to shorten development time as well as improve software quality. The VLAB/IMP-TASimulator is one of the latest software development tools for the Renesas R-Car V3M and is part of Renesas autonomy concept, which was announced in April 2017.

“Our goal is to provide a comprehensive, unified, and easy-to-use software development environment to all automotive system developers using R-Car SoCs,” said Jean-Francois Chouteau, Vice President, Global ADAS Center, Renesas Electronics Corporation. “The VLAB technology from ASTC is an important building block to speed up the development of ADAS software on the Renesas autonomy Platform.”

“We have a longstanding relationship with Renesas and are pleased to collaborate on their Renesas autonomy Platform to further accelerate software development for ADAS and automated driving,” said Hiroshi Yoshizawa, Australian Semiconductor Technology Company K.K. Vice President. “We have worked with Renesas on applying VLAB technology to model the R-Car V3M architecture, function, and timing, enabling R-Car V3M customers to bring new ADAS applications to market quickly with high quality and strong reliability.”

VLAB-IMP-TASimulator VP Block Diagram
VLAB-IMP-TASimulator VP Block Diagram

In ADAS and automated driving systems, algorithm development, including object detection and recognition to estimate the position of the vehicle, has become more complex and larger scaled, and algorithm development by PC has become the standard. However, it is difficult to port PC-developed algorithms to embedded software that deeply depends on hardware architecture. This makes it essential to have a development environment that enables a smooth transition or integration between the algorithm development phase and the embedded software development phase.

To address this need, Renesas and ASTC have jointly developed the VLAB/IMP-TASimulator VP, which enables embedded software development for the R-Car V3M using the PC only. ASTC’s core technology, VLAB, simulates target hardware on the PC to enable system developers to develop embedded software only with a PC, eliminating the use of actual hardware. This enables system developers to check and control the hardware on a virtual environment displayed on the PC. In addition, the VP can efficiently detect defects in the developed software. By using the VLAB/IMP-TASimulator, system developers can develop high-quality software in less than half the development time.

Key features of the VLAB/IMP-TASimulator

Significant reduction in software development period by reproducing R-Car V3M’s IMP-X5 image recognition engine on PC

The new VP reproduces the IMP-X5’s built-in 64 thread MIMD processor on the PC, which enables debugging such as step execution, break, and variable reference of software written in C language dedicated to multithreaded programming. This reduces the software development period dramatically compared to when not using this virtual environment.

ASTC’s timing-correlated simulation technology enables an accurate estimation of the hardware processing time

The new VP includes a timing-correlated simulator that accurately grasps and reflects the hardware key timing and efficiently simulates the IMP-X5 by modeling the complicated timing behaviour of the cache, bus, processor and other major components. This allows system developers to estimate the hardware processing time at least 100 times faster than the currently used cycle-based simulator.


The VLAB/IMP-TASimulator VP will be available from Q1 2018 from ASTC and VLAB Works.