Plural Nano DSP ADCs – Silanna has added a DSP function block to its Plural™ Nano ADCs, the world’s smallest data converters.
The integration of the feature-rich DSP shrinks or completely eliminates the need for an FPGA to perform down-stream processing, which enables even greater reductions in board space. It also reduces system complexity and cost.
The Plural Nano DSP is available in resolutions 12-, 14- and 16-bit and with sample rates from 5 to 250 Msps. Like the Plural Nano, the Plural Nano DSP is available in two package sizes: 3.4×3.4 mm (12-bit single/dual, 14- and 16-bit single channel) and 3.7×3.7 mm (14- and 16-bit dual channel) packages.
These packages are 83% and 86% smaller than competing devices with sample rates over 125Msps, which are almost-universally sized 9×9 mm or larger. They are also 45% and 54% smaller than competing 125 Msps devices, which are 5×5 mm or larger.
These PCB size savings are before any down-stream processing is considered. And despite its smaller size, the Plural Nano DSP is able to perform the same range of functions as its larger Plural DSP sister devices, including decimation, digital down-conversion (DDC), interleaving, and IQ-mismatch correction.
“Adding the feature-rich DSP function to the ultra-small Nano family is a significant feat for the ADC team and will be of huge benefit to our customers,” said Randy Wayland, VP of Data Converter Products at Silanna. “With signal conditioning and channel correction able to be done directly on the converter, even when using these super-small devices, many applications will be able to lose completely, or significantly reduce, FPGA requirements, which further cuts board space, cuts cost and cuts complexity.”
At launch, 24 12-, 14- and 16- bit Nano ADCs are available with the DSP function, with these taking the total number of Plural Nano devices above 170. The company will also announce additional resolutions in the coming months this year.
Like the original lineup of Plural ADCs, the Nano family of data converters combines a pipeline ADC core with on-chip reference and clock management circuitry, supports LVDS and CMOS outputs and has an operational temperature range of -40 to +85oC.
The Plural Nano product family and EVKs can be obtained through Silanna’s authorized network of distributors. To register interest, download specifications, and order samples, please visit https://silanna.com/plural-nano-bga/.
